Copper is used extensively to form the metal interconnect lines in integrated circuits. The metal interconnect lines are used to interconnect the electronic devices formed in the semiconductor material. These electronic devices include transistors, capacitors, inductors, and resistors. The metal interconnect lines are formed in dielectric layers that are formed above the semiconductor material. Copper lines are formed using a damascene type process. In a damascene process trenches are first formed in the dielectric layers. A barrier layer is then formed in trench. The barrier layer is necessary to prevent the diffusion of copper into the dielectric layer. Typical barrier layers include titanium nitride, tantalum, tantalum nitride, and other suitable material. A copper seed layer is then formed on the barrier layer using a physical vapor deposition (PVD) process. Electrochemical deposition (ECD) is then used to fill the remaining opening in the trench with copper. Electrochemical deposition (ECD), also known as electroplating, allows “superconformal” film formation, leading to defect-free fill of patterned structures. A potential is applied between two electrodes (anode, cathode) that are immersed into a conductive solution (electrolyte) containing copper (Cu) ions. ECD requires a conductive surface (cathode) to reduce Cu2+ to Cu0 and initiate nucleation and growth of Cu. Therefore, a thin layer of Cu seed is typically deposited across the entire wafer surface/features prior to ECD, serving as cathode during ECD Cu. Provided a conformal Cu seed layer, uniform potential (current), and sufficient Cu2+ concentration (electron-transfer controlled deposition) within patterned structures, ECD allows for conformal film formation and feature fill. “Superconformal” film formation and feature fill (“superfill”) can be achieved by the use of additives that lead to a higher deposition rate at the bottom than on the sidewall of patterned features. Additives are also known to influence ECD Cu recrystallization processes that occur at room temperature. During this room-temperature self-annealing (RTSA), an increase in ECD Cu grain size (and an enhancement in crystallinity) has been observed over time at room temperature along with a decrease in film resistivity and (compressive) stress. For direct-plating of ECD Cu on (“seedless”) barrier materials, potential (current) wave forms as well as electrolyte composition (e.g., sulfate-, fluoroborate-, citrate-, or ethylenediaminetetraacetate-based chemistries, etc.) and type of additives need to be tailored to achieve optimal deposition conditions for ECD Cu nucleation and growth.
The copper seed layer is necessary because copper will not electroplate directly to the typical barrier layers. An example of a trench is shown in FIG. 1(a). The electronic devices in the semiconductor 10 have been omitted for clarity. As described above, a dielectric 20 is formed above the semiconductor 10. A barrier layer 30 and a copper seed layer 40 are formed in the trench 5 prior to the filling of the trench 5 with copper 50.
As devices dimensions shrink the width of the trench used to form the copper lines will also shrink. Shown in FIG. 1(b) is the case of a trench 7 with reduced width. The barrier layer 30 and copper seed layer 40 are formed in the trench 7 as shown in the Figure. These layers reduce the width of the trench prior to the filling of the trench using copper electroplating. During the electroplating process the narrow opening of the trench often leads to the creating of voids 60 in the copper 50. The presence of such voids 60 in the copper 50 will increase the resistance of the interconnect lines and lead to unreliable integrated circuit performance. There is therefore a great need for a method of forming copper interconnect lines in narrow trenches without forming voids. The instant invention addresses this need.